1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor integrated circuit devices. More specifically, this invention relates to the manufacture of high performance semiconductor transistors having reduced channel lengths. Even more specifically, this invention relates to the manufacture of high performance semiconductor transistors having reduced channel lengths and self-aligned lightly doped drain (LDD) extensions.
2. Discussion of the Related Art
Several performance enhancers for modern semiconductor devices are critical as high performance transistors are scaled to further enhance performance. For example, as the channel length of the transistor is reduced, features such as the lightly doped-drain (LDD) extension regions have been added to solve some of the problems associated with short-channel effects that have resulted from the shortened channel length.
A major obstacle to the formation of very short channel devices is the limitation of commercially available sources of illumination for use in manufacturing processes. The non-availability of illumination devices that would allow the printing of very small features on a layer of photoresist that are then transferred to a further layer, such as a layer of polysilicon. For a "classic" gate structure, the photoresist pattern is first reduced by a well-known resist trimming technique. However, this reduction also reduces the amount of polysilicon, thus increasing the resistance of the device. To then remedy this problem, thicker layers of polysilicon are deposited. However, thicker polysilicon increases the aspect ratio between two adjacent features that results in a non-uniform etch. Another problem of the classic gate manufacturing method is that the upper surface "landing pad" is too small for the next layer, such as an interconnect layer, to properly align upon. The remedy the small upper landing surface, "T" or "notched" gates have been attempted. However, these irregular shaped features require angular or lateral implants to form LDD under the notches. These angular or lateral implants produce poor implant profiles and the resultant overlapping capacitances are not optimal.
Therefore, what is needed is a method to utilize currently commercially available illumination sources, materials, and equipment in such a way that well understood processes can continue to be used to manufacture high performance semiconductor devices.